Communication Dans Un Congrès Année : 2005

A 23-24 GHz low power frequency synthesizer in 0.25 μm SiGe

H. Lapouyade
  • Fonction : Auteur
J.B. Begueret
  • Fonction : Auteur
A. Cathelin
  • Fonction : Auteur
D. Belot
  • Fonction : Auteur

Résumé

This paper presents the design and the experimental measurements of a 24 GHz fully integrated fractional PLL, for ISM band, with a new low power prescaler. This circuit is implemented in a 0.25 mu m SiGe:C process from STMicroelectronics (BiCMOS7RF). The PLL power dissipation is 170 mW and fulfills a 23.7 to 24.9 GHz frequency locking range, while exhibiting a phase noise of -100 dBc/Hz at 100 KHz from the carrier. The simulated PLL unity-gain bandwidth is 36 MHz, with a phase margin of 54 degrees. The PLL uses a new latch-based prescaler (SRO) which exhibits a power dissipation of 0.68 GHz/mW
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Dates et versions

in2p3-00370534 , version 1 (24-03-2009)

Identifiants

  • HAL Id : in2p3-00370534 , version 1

Citer

O. Mazouffre, H. Lapouyade, J.B. Begueret, A. Cathelin, D. Belot, et al.. A 23-24 GHz low power frequency synthesizer in 0.25 μm SiGe. 13th European Gallium Arsenide and Other Compound Semiconductors Application Symposium, Oct 2005, Paris, France. pp.533-536. ⟨in2p3-00370534⟩
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