Common Control and Readout Board for the Calorimeter and Tracker Front-End Electronics of the SuperNEMO Experiment
Abstract
SuperNEMO (SN) is the next-generation (0νββ) experiment based on a tracking plus calorimetry technique. The construction of the demonstrator has started in 2012 and its installation is expected in 2014 in LSM underground laboratory (France). The SN experiment is designed to measure both energy and time of flight of each beta particle emitted from ββ decays. The demonstrator is made of a calorimeter (700 channels) and a tracking detector (6000 channels). These detectors front-end electronics use an unified architecture based on six similar crates that each host up to 20 Front-End Boards (FEB) and one SN_CROB board. The FEBs perform the acquisition of the detector channels. The SN_CROB board gathers the front-end data from the calorimeter or tracker FEBs and sends them through Ethernet link to the data acquisition (DAQ) system. It extracts the Trigger Primitive (TP) from the front-end data and sends them through serial link to the Trigger Board (SN_TB). Moreover SN_CROB distributes the clock, the trigger and the control signals for all the boards in a crate. It can also provide its own clock. On each SN_CROB, four Fe-PGA each receive the data from five FEBs and one Ctrl-PGA (the board driver) performs the actions which are not specific to a data channel and is in charge of copying and sending through the experiments control system the data stored into the Fe-PGA for spying purpose. With respect to trigger, we extract the TP from each Fe-PGA and send them to Ctrl-PGA. Then from the Ctrl-PGA, we compute the TP and build the Crate Trigger Word (CTW) which contains informations about hit multiplicity, particle zoning and event identification. It is sent to the SN_TB through serial link. Concerning data, they are extracted from each Fe-PGA and sent to Ctrl-PGA which then sends them to the DAQ through Gigabit Ethernet transceiver. The communication between FPGA is ensured by a dedicated protocol based on a parallel interface for byte transmission.